Line codes

Why line coding exists

A sender and receiver must agree which physical conditions represent data and when to sample them. An ideal code would use little bandwidth, contain enough changes to recover a clock, have no long-term DC voltage, tolerate noise, reveal errors and carry many bits per symbol. No code gets every property for free.

• Transition density: regular changes let the receiver recover timing. A long flat signal makes bit boundaries uncertain.
• DC balance: roughly equal positive and negative energy avoids a DC component that transformers and AC-coupled links cannot pass.
• Bandwidth: faster transitions and more symbols require more channel bandwidth.
• Noise margin: levels must remain distinguishable after attenuation, interference and distortion.
• Efficiency: coding may add extra transmitted symbols to guarantee useful properties.

A bit is information; a symbol is one physical signalling interval. A two-level symbol can represent one bit. Four levels can represent two bits, but the smaller spacing between levels makes noise more troublesome.

NRZ-L and NRZ-I

NRZ-L — Non-Return-to-Zero Level

One level means 0 and another means 1. The signal holds that level for the whole bit and does not return to a neutral level between bits. It is simple and bandwidth-efficient, but long runs of identical bits contain no transitions for clock recovery and can create a large DC component.

NRZ-I — Non-Return-to-Zero Inverted

Information is represented by a change rather than an absolute level. In the common convention, a 1 causes a transition at the start of the bit and a 0 causes none. Reversing both wires no longer swaps ones and zeros, but a long run of zeros still has no timing transitions.

Some standards choose the opposite bit convention, so always read the code’s specific definition.

RZ and Manchester family

RZ — Return-to-Zero

The signal represents a bit during only part of its interval and then returns to zero. That adds transitions and makes timing easier than plain NRZ, but uses more bandwidth and often more signalling energy. Polar RZ can use positive and negative pulses; unipolar RZ uses a pulse for one bit value and zero for the other.

Manchester encoding

Every bit has a transition in its middle, which embeds the clock. The direction of that transition represents the bit value. Different conventions reverse which direction means 0, so context matters. Classic 10 Mbit/s Ethernet uses Manchester coding.

The guaranteed transitions give excellent clock recovery and no lasting DC offset, but the signalling rate is twice the bit rate, demanding roughly twice the bandwidth of NRZ.

Differential Manchester

There is always a mid-bit transition for clocking. Whether there is also a transition at the beginning carries the data—commonly a start transition means 0 and no start transition means 1. Because meaning depends on change rather than voltage polarity, swapping the wires does not corrupt the data. It was used by Token Ring.

AMI and pseudoternary

AMI — Alternate Mark Inversion

A binary 0 is zero voltage. Successive 1s alternate positive, negative, positive, negative. That alternating polarity largely removes DC and allows a receiver to detect some errors: two same-polarity marks in sequence are a bipolar violation.

Long runs of zeros still contain no transition, so telecom systems add scrambling or deliberate violation patterns such as B8ZS or HDB3 to maintain timing.

Pseudoternary

Pseudoternary reverses the roles: binary 1 is zero voltage, while successive binary 0s alternate positive and negative. Its electrical advantages and long-run problem mirror AMI. “Ternary” means it uses three possible levels: positive, zero and negative.

MLT-3 — Multi-Level Transmit-3

MLT-3 cycles among three levels 0 → + → 0 → − → 0. A 1 advances to the next level; a 0 holds the current level. The highest-frequency repeating pattern therefore takes four 1 bits to complete a cycle, greatly reducing high-frequency energy compared with NRZ.

MLT-3 alone still permits an endless flat signal if the data contains zeros. 100BASE-TX first applies 4B5B to guarantee transitions, then NRZ-I logic and MLT-3 physical signalling. This layering is why several names can all correctly describe one Ethernet link.

2B1Q, 4B3T and 8B6T

These names state how input bits map to output symbols. More physical levels can carry more information per symbol, reducing the required symbol rate, but each level has a smaller noise margin.

The raw combination count must be large enough: three ternary symbols provide 3³ = 27 patterns for 16 possible 4-bit inputs; six provide 3⁶ = 729 patterns for 256 bytes. Spare patterns let the designer optimise balance or reserve invalid/control combinations.

Block codes: 4B5B, 8b/10b and 64b/66b

A block code maps data to a longer codeword before the final electrical or optical encoding. The extra combinations enforce useful signal properties and can represent control symbols.

4B5B

Every 4 data bits become a selected 5-bit word with enough transitions and no more than a controlled run of zeros. Efficiency is 4/5, or 80%: 100 Mbit/s of data becomes 125 Mbaud of coded bits. 100BASE-TX combines 4B5B with MLT-3; FDDI used it with NRZ-I.

8b/10b

Every byte becomes a 10-bit symbol selected for transition density and near-zero running disparity—the cumulative difference between transmitted ones and zeros. Special control symbols support framing and link management. Efficiency is 80%, meaning 25% signalling overhead relative to payload. It is used by early PCI Express generations, Fibre Channel, Serial ATA and many serial links.

64b/66b

Two synchronisation bits identify a 64-bit payload as data or control. The payload is scrambled so its bits look random and usually contain transitions. Efficiency is 64/66 ≈ 96.97%, only about 3.125% overhead relative to payload. A scrambler gives excellent statistics but does not impose the strict short-term DC bounds of 8b/10b. High-speed Ethernet uses 64b/66b and related larger block schemes.

PAM-4 and PAM-5

Pulse Amplitude Modulation encodes symbols as amplitude levels. Despite often appearing in lists of line codes, PAM names the physical modulation alphabet rather than the complete coding system around it.

PAM-4

Four amplitude levels carry two bits per symbol. That halves the symbol rate required for a given bit rate compared with two-level signalling, easing the channel bandwidth requirement. The cost is only one-third as much level spacing for the same total swing, so PAM-4 needs a cleaner channel, powerful equalisation and forward error correction. It is used in modern high-speed Ethernet and PCIe 6.0.

The actual bit-to-level assignment is often Gray coded so adjacent-level mistakes alter only one bit.

PAM-5

Five amplitude levels provide four data levels plus an extra level/state capacity used by the full coding scheme. 1000BASE-T transmits simultaneously over four wire pairs using a sophisticated four-dimensional, five-level system commonly described as 4D-PAM5, with trellis coding, echo cancellation and crosstalk cancellation. It is not simply “two bits mapped independently to one of five voltages.”

How to compare line codes

A standards name often describes a chain rather than one code. Data might be scrambled, block-coded, protected with error correction, mapped to PAM levels and then equalised at the receiver. Ask which layer a term describes before comparing it with another.